Found 21 results
Author Title Type [ Year
] Filters: First Letter Of Last Name is Z [Clear All Filters]
Virtual-Source Modeling of N-polar GaN MISHEMTS,
, 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), p.1-4, (2019)
Scaling trends for picojoule-per-bit WDM photonic interconnects in CMOS SOI and FinFET processes,
, Journal of Lightwave Technology, Volume 34, Number 11, p.2730–2742, (2016)
A 1.1-Gbit/s 10-GHz outphasing modulator with 23-dBm output power and 60-dB dynamic range in 45-nm CMOS SOI,
, IEEE Transactions on Microwave Theory and Techniques, Volume 63, Number 7, p.2289–2300, (2015)
A low-power, high-speed, 9-channel germanium-silicon electro-absorption modulator array integrated with digital CMOS driver and wavelength multiplexer,
, Optics express, Volume 22, Number 10, p.12289–12295, (2014)
A 25-Gb/s monolithic optical transmitter with micro-ring modulator in 130-nm SoI CMOS,
, IEEE Photonics Technology Letters, Volume 25, Number 19, p.1901–1903, (2013)
Energy efficiency optimization through codesign of the transmitter and receiver in high-speed on-chip interconnects,
, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22, Number 4, p.938–942, (2013)
A monolithic 25-Gb/s transceiver with photonic ring modulators and Ge detectors in a 130-nm CMOS SOI process,
, IEEE Journal of Solid-State Circuits, Volume 47, Number 6, p.1309–1322, (2012)
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links,
, IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 1, Number 9, p.1406–1420, (2011)
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links,
, IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 1, Number 9, p.1406–1420, (2011)
A fully-integrated optical duobinary transceiver in a 130nm SOI CMOS technology,
, 2011 IEEE Custom Integrated Circuits Conference (CICC), p.1–4, (2011)
High-speed and low-power on-chip global link using continuous-time linear equalizer,
, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, p.5–8, (2010)
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling,
, Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, p.69–76, (2010)
Prediction and comparison of high-performance on-chip global interconnection,
, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 7, p.1154–1166, (2010)
Design methodology of high performance on-chip global interconnect using terminated transmission-line,
, 2009 10th International Symposium on Quality Electronic Design, p.451–458, (2009)
Design methodology of high performance on-chip global interconnect using terminated transmission-line,
, 2009 10th International Symposium on Quality Electronic Design, p.451–458, (2009)
On-chip global clock distribution using directional rotary traveling-wave oscillator,
, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, p.251–254, (2009)
Prediction of high-performance on-chip global interconnection,
, Proceedings of the 11th international workshop on System level interconnect prediction, p.61–68, (2009)
Low power passive equalizer design for computer memory links,
, 2008 16th IEEE Symposium on High Performance Interconnects, p.51–56, (2008)
Low power passive equalizer design for computer memory links,
, 2008 16th IEEE Symposium on High Performance Interconnects, p.51–56, (2008)
On-chip bus signaling using passive compensation,
, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, p.33–36, (2008)
On-chip bus signaling using passive compensation,
, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, p.33–36, (2008)