Found 34 results
Author Title Type [ Year
] Filters: First Letter Of Last Name is D [Clear All Filters]
A Fully Integrated O-band Coherent Optical Receiver Operating up to 80 Gb/s,
, 2021 IEEE Photonics Conference (IPC), p.1-2, (2021)
A Case for Digital Beamforming at mmWave,
, arXiv preprint arXiv:1901.08693, (2019)
A Case for Digital Beamforming at mmWave,
, arXiv preprint arXiv:1901.08693, (2019)
Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design,
, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), p.235–240, (2019)
Compact series power combining using subquarter-wavelength baluns in silicon germanium at 120 GHz,
, IEEE Transactions on Microwave Theory and Techniques, Volume 66, Number 11, p.4844–4859, (2018)
High-power, high-efficiency digital polar doherty power amplifier for cellular applications in SOI CMOS,
, 2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR), p.18–20, (2016)
Series power combining: Enabling techniques for Si/SiGe millimeter-wave power amplifiers,
, 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), p.116–119, (2016)
A 22 dBm, 0.6 mm$^2$ D-Band SiGe HBT Power Amplifier Using Series Power Combining Sub-Quarter-Wavelength Baluns,
, 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), p.1–4, (2015)
A 45-GHz Si/SiGe 256-QAM transmitter with digital predistortion,
, 2015 IEEE MTT-S International Microwave Symposium, p.1–3, (2015)
A high-linearity, 30 GS/s track-and-hold amplifier and time interleaved sample-and-hold in an InP-on-CMOS process,
, IEEE Journal of Solid-State Circuits, Volume 50, Number 11, p.2692–2702, (2015)
$ Q $-Band Spatially Combined Power Amplifier Arrays in 45-nm CMOS SOI,
, IEEE Transactions on Microwave Theory and Techniques, Volume 63, Number 6, p.1937–1950, (2015)
Transmission of signals with complex constellations using millimeter-wave spatially power-combined CMOS power amplifiers and digital predistortion,
, IEEE Transactions on Microwave Theory and Techniques, Volume 63, Number 7, p.2364–2374, (2015)
A Watt-Class, High-Efficiency, Digitally-Modulated Polar Power Amplifier in SOI CMOS,
, 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), p.1–4, (2015)
Active millimeter-wave phase-shift Doherty power amplifier in 45-nm SOI CMOS,
, IEEE Journal of Solid-State Circuits, Volume 48, Number 10, p.2338–2350, (2013)
Analysis and design of stacked-FET millimeter-wave power amplifiers,
, IEEE Transactions on Microwave Theory and Techniques, Volume 61, Number 4, p.1543–1556, (2013)
High-speed, high-efficiency millimeter-wave transmitters at 45 GHz in CMOS,
, 2013 IEEE MTT-S International Microwave Symposium Digest (MTT), p.1–3, (2013)
A W-band stacked FET power amplifier with 17 dBm P sat in 45-nm SOI MOS,
, 2013 IEEE Radio and Wireless Symposium, p.256–258, (2013)
A 34% PAE, 18.6 dBm 42–45GHz stacked power amplifier in 45nm SOI CMOS,
, 2012 IEEE Radio Frequency Integrated Circuits Symposium, p.57–60, (2012)
A 45GHz Doherty power amplifier with 23% PAE and 18dBm output power, in 45nm SOI CMOS,
, 2012 IEEE/MTT-S International Microwave Symposium Digest, p.1–3, (2012)
Linear operation of high-power millimeter-wave stacked-FET PAs in CMOS SOI,
, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), p.686–689, (2012)
Modeling and analysis of power distribution networks in 3-D ICs,
, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 21, Number 2, p.354–366, (2012)
$ Q $-band and $ W $-band power amplifiers in 45-nm CMOS SOI,
, IEEE Transactions on Microwave Theory and Techniques, Volume 60, Number 6, p.1870–1877, (2012)
A 45-GHz SiGe HBT amplifier at greater than 25% efficiency and 30 mW output power,
, 2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, p.25–28, (2011)
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links,
, IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 1, Number 9, p.1406–1420, (2011)
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links,
, IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 1, Number 9, p.1406–1420, (2011)
A Q-band amplifier implemented with stacked 45-nm CMOS FETs,
, 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), p.1–4, (2011)
Prediction and comparison of high-performance on-chip global interconnection,
, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 7, p.1154–1166, (2010)
Design methodology of high performance on-chip global interconnect using terminated transmission-line,
, 2009 10th International Symposium on Quality Electronic Design, p.451–458, (2009)
Design methodology of high performance on-chip global interconnect using terminated transmission-line,
, 2009 10th International Symposium on Quality Electronic Design, p.451–458, (2009)
Prediction of high-performance on-chip global interconnection,
, Proceedings of the 11th international workshop on System level interconnect prediction, p.61–68, (2009)
Low power passive equalizer design for computer memory links,
, 2008 16th IEEE Symposium on High Performance Interconnects, p.51–56, (2008)
Low power passive equalizer design for computer memory links,
, 2008 16th IEEE Symposium on High Performance Interconnects, p.51–56, (2008)
On-chip bus signaling using passive compensation,
, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, p.33–36, (2008)
On-chip bus signaling using passive compensation,
, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, p.33–36, (2008)