] Energy efficiency optimization through codesign of the transmitter and receiver in high-speed on-chip interconnects,
, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22, Number 4, p.938–942, (2013)
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links,
, IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume 1, Number 9, p.1406–1420, (2011)
High-speed and low-power on-chip global link using continuous-time linear equalizer,
, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, p.5–8, (2010)
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling,
, Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, p.69–76, (2010)
Prediction and comparison of high-performance on-chip global interconnection,
, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 7, p.1154–1166, (2010)
Design methodology of high performance on-chip global interconnect using terminated transmission-line,
, 2009 10th International Symposium on Quality Electronic Design, p.451–458, (2009)
On-chip global clock distribution using directional rotary traveling-wave oscillator,
, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, p.251–254, (2009)
Prediction of high-performance on-chip global interconnection,
, Proceedings of the 11th international workshop on System level interconnect prediction, p.61–68, (2009)
Low power passive equalizer design for computer memory links,
, 2008 16th IEEE Symposium on High Performance Interconnects, p.51–56, (2008)
On-chip bus signaling using passive compensation,
, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, p.33–36, (2008)