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Prediction and comparison of high-performance on-chip global interconnection,
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Design methodology of high performance on-chip global interconnect using terminated transmission-line,
, 2009 10th International Symposium on Quality Electronic Design, p.451–458, (2009)
Prediction of high-performance on-chip global interconnection,
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Low power passive equalizer design for computer memory links,
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On-chip bus signaling using passive compensation,
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